发明名称 A cache arrangement
摘要 <p>A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.</p>
申请公布号 GB201112976(D0) 申请公布日期 2011.09.14
申请号 GB20110012976 申请日期 2011.07.28
申请人 STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED 发明人
分类号 主分类号
代理机构 代理人
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