发明名称
摘要 <p>An integrated circuit (1) receives an external clock signal (CK-ext) and in addition has a random generator (2) which produces a random clock signal (CK-al). The external and random clock signals are applied to a switching circuit (3). The switching circuit (3) is controlled by signals (K) from a group of circuits (5) including memories, data and processors and operates to select either the external or random clock signal for entry to the internal clock signal generator (4). The clock signal selection is such that the external signal is only used for external synchronisation.</p>
申请公布号 JP4773412(B2) 申请公布日期 2011.09.14
申请号 JP20070259733 申请日期 2007.10.03
申请人 发明人
分类号 G06F1/04;G06K19/07;G06F1/06;G06F1/08;G06F21/06;G06K17/00;G06K19/073 主分类号 G06F1/04
代理机构 代理人
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