发明名称 |
Semiconductor integrated circuit with multi-cut via and automated layout method for the same |
摘要 |
A semiconductor integrated circuit according to an embodiment of the invention includes a single-cut via 60 and a multi-cut via 30 that includes a first via 30a and a second via 30b. An overhang (OHa or OHb) with respect to at least one of the first via 30a and the second via 30b is smaller than an overhang OH with respect to the single-cut via 60.
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申请公布号 |
US8020133(B2) |
申请公布日期 |
2011.09.13 |
申请号 |
US20080076637 |
申请日期 |
2008.03.20 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
NISHIMUDA KEIICHI |
分类号 |
G06F17/50;H01L23/522 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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