| 摘要 |
A nonvolatile memory device having a memory cell array configured to include a number of memory cells coupled to a bit line, a control circuit configured to output a code signal in response to a verification operation command signal during a verification operation being performed, a page buffer operation voltage generator configured to generate a precharge signal and a sense signal in response to the code signal, and a page buffer configured to precharge the bit line in response to the precharge signal and to sense data programmed into the memory cell in response to the sense signal. A sense signal having a sequentially lowered voltage level is outputted in response to the verification operation being repeatedly performed.
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