发明名称 Leakage power reduction in CMOS circuits
摘要 A field effect transistor includes a source region and a drain region in contact with a channel region. The source and drain regions are formed in insulating pockets that cause the source and drain regions to be electrically isolated from the substrate, thereby minimizing junction capacitance and device crosstalk. The structures that define the insulating pockets can be insulating layers formed in one or more wells in the substrate, or can be a blanket insulating formed over the substrate in which a well is formed to contain the transistor.
申请公布号 US8018003(B2) 申请公布日期 2011.09.13
申请号 US20050139255 申请日期 2005.05.27
申请人 SYNOPSYS, INC. 发明人 PATIL CHANDRASHEKHAR V.
分类号 H01L29/76 主分类号 H01L29/76
代理机构 代理人
主权项
地址