| 摘要 |
A test apparatus provided in common for a plurality of memories under test, comprising an address generating section that sequentially generates addresses to be tested in the memories under test and a plurality of buffer memories that are provided to correspond respectively to the memories under test and that each store addresses to be independently supplied to the corresponding memory under test. The test apparatus (i) compares block data output by a memory under test in response to a read command to an expected value of this block data, for each generated address, (ii) sequentially stores, in the corresponding buffer memory and in response to detection of a discrepancy in the comparison, the address generated for reading the block data, and (iii) writes, in parallel to the plurality of memories under test, disable data that includes, as individual addresses, the addresses stored in the buffer memory.
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