| 摘要 |
PROBLEM TO BE SOLVED: To effectively reduce the packaging cost for manufacture of a chip-scale semiconductor device package. SOLUTION: The chip-scale semiconductor device package 20 includes a chip 22, an insulating substrate 21 having a through hole 211, a first metal layer 23, a second metal layer 24 and an insulating layer 25. The first metal layer 23 is on a first surface 212 of the insulating substrate 21 and a first opening 2111 of the through hole 211. The insulating layer 25 is overlaid on a second surface 213 of the insulating substrate 21 and surrounds a second opening 2111 of the through hole 211. The second metal layer 23 is on the insulating layer 25 and the second opening 2111. The chip 22 is in the through hole 2111 and includes a first electrode 221 and a second electrode 222. The first electrode 221 is electrically connected to the first metal layer 23, and the second electrode 222 is electrically connected to the second metal layer 24. COPYRIGHT: (C)2011,JPO&INPIT
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