发明名称 |
NOVEL SWITCHED PHASE AND FREQUENCY DETECTOR BASED DPLL CIRCUIT WITH EXCELLENT WANDER AND JITTER PERFORMANCE AND FAST FREQUENCY ACQUISITION |
摘要 |
Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.
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申请公布号 |
US2011215873(A1) |
申请公布日期 |
2011.09.08 |
申请号 |
US20100715749 |
申请日期 |
2010.03.02 |
申请人 |
CISCO TECHNOLOGY, INC. |
发明人 |
MONTREUIL LEO;MCKINNEY LARRY STEPHEN;AO JIENING;JENKINS JOEL PAUL |
分类号 |
H03L7/00 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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