| 摘要 |
A phase locked loop circuit according to the present invention includes a selector that selects an input clock, a 1/m frequency divider that divides a frequency of the input clock, a 1/n frequency divider that divides a frequency of a feedback clock, a phase difference detector, a first voltage controlled oscillator that includes a first voltage holding circuit, a second voltage controlled oscillator that includes a second voltage holding circuit, and a selection circuit that outputs any output of the first and second voltage controlled oscillators as an output clock and outputs any output of the first and second voltage controlled oscillators as a feedback clock. The input clock is switched when the voltage controlled oscillator in a holding mode generates the output clock and the voltage controlled oscillator in a normal mode generates the feedback clock.
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