DATA PROCESSOR, SEMICONDUCTOR DEVICE, AND DATA PROCESSING SYSTEM

摘要

PROBLEM TO BE SOLVED: To provide a data processor including an external bus interface function which can easily set delay in clock-synchronized data reading from a plurality of external devices having different analog characteristics of external interfaces respectively, has high adaptability and can quickly switch delay time. SOLUTION: An external bus interface control circuit for controlling delay of read data input from an external data terminal and controlling latch timing of the delay-controlled data is adopted. The latch timing is controlled by selecting one of outputs from a plurality of first delay circuits for delaying an internal clock signal to be output to the outside via a clock output buffer on the basis of a chip selection signal and providing the selected output as the latch clock of a latch circuit. The data delay is controlled by selecting one of outputs from a plurality of second delay circuits for delaying read data input from a data terminal on the basis of the chip selection signal and providing the selected output to the latch circuit as data to be latched. COPYRIGHT: (C)2011,JPO&INPIT