发明名称 |
STRUCTURE AND METHOD TO FABRICATE pFETS WITH SUPERIOR GIDL BY LOCALIZING WORKFUNCTION |
摘要 |
A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.
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申请公布号 |
US2011215412(A1) |
申请公布日期 |
2011.09.08 |
申请号 |
US20100717375 |
申请日期 |
2010.03.04 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
PEI CHENGWEN;BOOTH, JR. ROGER A.;CHENG KANGGUO;ERVIN JOSEPH;TODI RAVI M.;WANG GENG |
分类号 |
H01L27/092;H01L21/22;H01L21/336;H01L21/8238 |
主分类号 |
H01L27/092 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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