| 摘要 |
A mechanism for efficient CAVLC coding in a hardware implementation of a H.264 coder is provided. In an embodiment of the present invention, multiple modular CAVLC engines that each process one sub-macroblock of data are used. An assembler engine that combines the CAVLC-encoded sub-macroblock data from each modular CAVLC engine to form a output bit-stream is also provided.
|
