| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a flip-flop circuit and a latch circuit which reduce current consumption caused by the level change of a clock signal. <P>SOLUTION: The flip-flop circuit is equipped with: a master latch 1; and a slave latch 2. In the master latch 1, a PMOS transistor P15 and an NMOS transistor N15 into which a clock signal CK is input, are shared between two cross-connected OR-NAND type composite gates. In the slave latch 2, a PMOS transistor P25 and an NMOS transistor N25 into which a clock signal CK is input are shared between two cross-connected AND-NOR type composite gates. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
