发明名称 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED CONDUCTOR AND METHOD OF MANUFACTURE THEREOF
摘要 A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a component connector on the substrate; forming a resist layer on the substrate with the component connector exposed; forming a vertical insertion cavity in the resist layer, the vertical insertion cavity isolated from the component connector or a further vertical insertion cavity, the vertical insertion cavity having a cavity side that is orthogonal to the substrate; forming a rounded interconnect in the vertical insertion cavity, the rounded interconnect nonconformal to the vertical insertion cavity; and mounting an integrated circuit device on the component connector.
申请公布号 KR20110098679(A) 申请公布日期 2011.09.01
申请号 KR20110017227 申请日期 2011.02.25
申请人 STATS CHIPPAC LTD. 发明人 YANG, DEOK KYUNG;AHN, SEUNG YUN
分类号 H01L23/48 主分类号 H01L23/48
代理机构 代理人
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