| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of improving data reading reliability by achieving a fast detection operation without using any column address circuit when a column where verification fails is identified. <P>SOLUTION: The semiconductor memory device includes: a plurality of holding circuits 30-1 to 33-n capable of holding first information F1<0:n> indicating presence or absence of a verification failure in a corresponding column; and a logical gate chain 50 including a plurality of first logical gates 51-0 to 51-n corresponding to respective columns and serially connected so as to output a logical level indicating presence or absence of a verification failure in any one of the columns to a next stage. The logical gate chain 50 is configured such that contents indicated by the logical levels PoF output from the first logical gates 51-0 to 51-n are reversed from the column where there is a verification failure. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
