发明名称 SERIAL ARCHITECTURE FOR HIGH ASSURANCE PROCESSING
摘要 A processing system (60) includes an input interface (62), a first processor (64), a second processor (66), and an output interface (68) arranged in a serial configuration. Each of the input interface (62), first processor (64), second processor (66), and output interface (68) computes a digest (92, 100, 110, and 114) using information, e.g., a unique parameter (94, 102, 112, 118), known only by that element (62, 64, 66, 68) and using information generated by that element (62, 64, 66, 68). The digests (92, 100, 110, and 114) are used to validate the integrity of payload data (86) processed by the system (60) to form processed data (104) and the system (60) only outputs the processed data (104) upon validation of data integrity. The serial configuration of system (60) may be implemented to provide high bit rate, redundant cryptographic services.
申请公布号 US2011213984(A1) 申请公布日期 2011.09.01
申请号 US20100713409 申请日期 2010.02.26
申请人 GENERAL DYNAMICS C4 SYSTEMS, INC. 发明人 ORLANDO GERARDO;KING DAVID R.;KRUMPOCH MARK;CUSTODIO EVAN
分类号 H04L9/32 主分类号 H04L9/32
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