CDR CIRCUIT

摘要

PROBLEM TO BE SOLVED: To satisfy both secure synchronization between input data and a regeneration clock and appropriate jitter reduction of the regeneration clock.

SOLUTION: A CDR (Clock Data Recovery) circuit includes: a gating circuit 2 for outputting a pulse when input data transit; a G-VCO (Voltage Controlled Oscillator with Gate) 3 for adjusting the phase of an output clock to correspond with timing of the output pulse of the gating circuit 2; a VCO (Voltage Controlled Oscillator) 4 for adjusting the phase of the output clock to correspond with timing of a clock output from the G-VCO 3; a flip-flop 1 performing data identification of the input data based on a regeneration clock output from the VCO 4; and a buffer amplifier 6a arranged between the output terminal of the G-VCO 3 and the input terminal of the VCO 4. The buffer amplifier 6a includes a drive power adjustment function of adjusting drive power in accordance with a drive power control signal input from the outside.

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