| 摘要 |
<P>PROBLEM TO BE SOLVED: To inspect a phase follow-up function of a CDR circuit in a serial interface circuit by a loopback test. <P>SOLUTION: In a semiconductor device, a PLL circuit 2 generates a clock 21 for reception and a clock 22 for transmission, based on a frequency-modulated reference clock 1. A serializer 3 serializes parallel data 33 at timing corresponding to the clock 22 for transmission for output. The CDR circuit 8 executes clock data recovery to reception data 20 to generate reproduction data 24, based on the clock 21 for reception. A deserializer 14 makes parallel the reproduction data 24. A loopback line 19 inputs serial data 18 outputted from the serializer 7 to the CDR circuit 8 as the reception data 20. <P>COPYRIGHT: (C)2011,JPO&INPIT |
