| 摘要 |
<P>PROBLEM TO BE SOLVED: To increase the accuracy of simulation by reproducing an effect of a depletion layer formed immediately beneath an intermediate node. <P>SOLUTION: A verification apparatus detects, from an equivalent circuit 400 as an NMOS circuit model, a parallel circuit comprising a junction resistance RJLG<SB>S</SB>and a junction capacitance CJG<SB>S</SB>, and a junction resistance RJLG<SB>D</SB>and a junction capacitance CJG<SB>D</SB>, and a connection resistance Rdep connecting the parallel circuit to a substrate electrode. The verification apparatus then calculates a first coefficient indicating an impact of the junction resistances RJLG<SB>S</SB>and RJLG<SB>D</SB>and connection resistance Rdep on amplitude variation, and calculates a second coefficient indicating an impact of the junction capacitances CJG<SB>S</SB>and CJG<SB>D</SB>and connection resistance Rdep on phase variation. A junction capacitance CJG (=CJG<SB>S</SB>=CJG<SB>D</SB>) is corrected with the sum of the first and second coefficients. <P>COPYRIGHT: (C)2011,JPO&INPIT |
