| 摘要 |
A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal.
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