| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of shortening testing time of scan test without increasing circuit scale of the semiconductor integrated circuit. SOLUTION: The semiconductor integrated circuit of the invention includes a scan chain circuit (20) and outcome evaluation circuits (30/31, 40, and 50). The scan chain circuit (20) takes in test data (S1-1, 2, ...) contained in scan-in data (SI) to perform scan test. The outcome evaluation circuits (30/31, 40, and 50) takes in the expected value (D1, D2, ...) of the scan test with same amount of data as the test data that is contained in scan-in data to evaluate the outcome of scan test. COPYRIGHT: (C)2011,JPO&INPIT
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