| 摘要 |
A clock driver outputs first and second preferably complementary clock signals coupled to substantially equal capacitive loads. Before each clock state change, the clock driver briefly shorts-together the first and second clock signals, to equalize change on capacitive loads, which each assume a potential midway between high and low power supply levels. Charge from the logic high clock signal can thus be used to raise logic low level clock line, and vice versa, rather than draw power supply current. Substantial energy savings on the order of C·V2·f is achieved, where C is effective capacitive load, V is power supply magnitude, and f is clock frequency. The clock driver includes first and second enhanced inverters (inverters that cannot enter short-circuit current mode) whose outputs are the first and second clock signals, and a transistor switch coupled between the inverter outputs. Turning on the transistor switch forces charge equalization.
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