| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase detection circuit which reduces the lag of two pulse signals generated based on a phase comparison of two clock signals as much as possible, and is reliably reset, and a PLL circuit having the phase detection circuit. <P>SOLUTION: A phase detection circuit includes a latch circuit that selects a preparation operation state before phase comparison or a circuit operation state after the phase comparison, to hold one of outputs used for generation of two pulse signals on an advance phase side and a delay phase side, based on an OR signal and an AND signal of two clock signals to be subjected to phase comparison. <P>COPYRIGHT: (C)2011,JPO&INPIT |
