发明名称 |
CIRCUIT AND TECHNIQUE FOR REDUCING PARITY BIT-WIDTHS FOR CHECK BIT AND SYNDROME GENERATION FOR DATA BLOCKS THROUGH THE USE OF ADDITIONAL CHECK BITS TO INCREASE THE NUMBER OF MINIMUM WEIGHTED CODES IN THE HAMMING CODE H-MATRIX |
摘要 |
A circuit and technique for reducing parity bit-widths for check bit and syndrome generation is implemented through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The circuit and technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.
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申请公布号 |
US2011209033(A1) |
申请公布日期 |
2011.08.25 |
申请号 |
US201113102522 |
申请日期 |
2011.05.06 |
申请人 |
UNITED MEMORIES, INC |
发明人 |
JONES, JR. OSCAR FREDERICK |
分类号 |
H03M13/15;G06F11/10 |
主分类号 |
H03M13/15 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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