| 摘要 |
A pulse sequence shaper with fixed pulse length equal to three clok cycles with adjustable interval and a period comprises a reversible counterdown binary counters having a clock input, integration/counterdown input, a synchronous parallel load enable input, loading data inputs, counting mode enable input, asynchronous reset input, overflow output, first and second OR elements, an inverter, a circuit comprising in series connected resistor and capacitor, a start-stop device comprising, a synchronous D flip-flop with asynchronous reset input, first and second AND elements. In addition, two JK-triggers are incorporated each of which having by two J and K inputs, "I" inputs of which are united, and asynchronous reset input, third element OR. |
