发明名称 Control data modification within a cache memory
摘要 A data processing system is provided with at least one processor 4, 6, a main memory 18 and a cache memory 14. Cache data within the cache memory 14 has validity data V and control data associated therewith. The control data controls access to the cached data. Program instructions executed by the processors 4, 6 control a cache controller 26 to modify the control data associated with the cached data while it remains stored within the cache memory 14 and remains valid. The control data may, for example, specify a security flags indicating whether access is restricted to secure processes or processors.
申请公布号 GB2449454(B) 申请公布日期 2011.08.24
申请号 GB20070009817 申请日期 2007.05.22
申请人 ARM LIMITED 发明人 PETER WILLIAM HARRIS;DONALD FELTON
分类号 G06F12/08;G06F12/12 主分类号 G06F12/08
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