发明名称 Data transfer between a master and slave
摘要 A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configured to output signals that are different to each other.
申请公布号 GB2444745(B) 申请公布日期 2011.08.24
申请号 GB20060024875 申请日期 2006.12.13
申请人 ARM LIMITED 发明人 NICOLAS CHAUSSADE;PIERRE MICHEL BROYER;PHILLIPE LUC
分类号 G06F13/40;G06F1/04;G06F13/42 主分类号 G06F13/40
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