| 摘要 |
Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.
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