发明名称 |
Iterative write pausing techniques to improve read latency of memory systems |
摘要 |
Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.
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申请公布号 |
US8004884(B2) |
申请公布日期 |
2011.08.23 |
申请号 |
US20090533548 |
申请日期 |
2009.07.31 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FRANCESCHINI MICHELE M.;LASTRAS-MONTANO LUIS A.;QURESHI MOINUDDIN K.;SRINIVASAN VIJAYALAKSHMI |
分类号 |
G11C11/00 |
主分类号 |
G11C11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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