发明名称 |
Logic transformation and gate placement to avoid routing congestion |
摘要 |
A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.
|
申请公布号 |
US8006210(B2) |
申请公布日期 |
2011.08.23 |
申请号 |
US20080014344 |
申请日期 |
2008.01.15 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BHAT CHAITRA M.;MADHWACHARYA CHANDRIKA;SUGAI ATSUSHI;YOKOTA TOSHIHIKO |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|