发明名称 Block redundancy implementation in hierarchical rams
摘要 The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.
申请公布号 US8004912(B2) 申请公布日期 2011.08.23
申请号 US20090491864 申请日期 2009.06.25
申请人 BROADCOM CORPORATION 发明人 TERZIOGLU ESIN;WINOGRAD GIL I.;AFGHAHI MORTEZA CYRUS
分类号 G11C29/00;G06F13/40;G11C7/06;G11C7/18;G11C11/419 主分类号 G11C29/00
代理机构 代理人
主权项
地址