| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce clock jitters of a semiconductor device, while limiting the increase in the circuit area thereof. <P>SOLUTION: In the semiconductor device having a circuit block which uses a reference clock signal as an operation clock in operation, and a circuit block which uses a clock signal obtained by n-dividing the frequency of the reference clock signal as the operation clock in operation; a delay circuit provides a predetermined delay to the reference clock signal; a selector selects one clock signal out of the reference clock signal and the delayed clock signal, according to a control signal and outputs the selected clock signal to the circuit block which uses the reference clock signal as the operation clock in operation; and then the amount of phase shift of the reference clock signal combining the phase changes due to power source noise is equalized for each period thus reducing clock jitter. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
