发明名称 PROCESS FOR FABRICATING HETEROSTRUCTURE WITH MINIMIZED STRESS
摘要 PROBLEM TO BE SOLVED: To provide a method of suppressing peeling at and the occurrence of a defect to an edge of a substrate during bonding of a hetero-substrate. SOLUTION: A process for fabricating a heterostructure comprises a step of bonding a first wafer 110 to a second wafer 120, the first wafer 110 having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer 120, and at least one bond-strengthening annealing step. The process is particularly characterized in that it comprises, after the bonding step and before the bond-strengthening annealing step, at least one trimming step in which the first wafer 110 is at least partially trimmed. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011159955(A) 申请公布日期 2011.08.18
申请号 JP20100235706 申请日期 2010.10.20
申请人 SOI TEC SILICON ON INSULATOR TECHNOLOGIES 发明人 VAUFREDAZ ALEXANDRE
分类号 H01L27/12;H01L21/02 主分类号 H01L27/12
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