ARCHITECTURE FOR SINGLE-STEPPING IN RESONANT CLOCK DISTRIBUTION NETWORKS
摘要
A resonant clock distribution network architecture is proposed that is capable of single-step operation through the use of selective control in the resonant clock drivers and the deployment of flip-flops that require the clock to remain stable for a sufficiently long time between any two consecutive state updates. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
申请公布号
WO2011046984(A3)
申请公布日期
2011.08.18
申请号
WO2010US52401
申请日期
2010.10.12
申请人
CYCLOS SEMICONDUCTOR INC.;PAPAEFTHYMIOU, MARIOS, C.;ISHII, ALEXANDER