发明名称 PACKAGING CONNECTION STRUCTURE OF ELECTRONIC COMPONENT
摘要 PROBLEM TO BE SOLVED: To solve the problem, wherein long-term reliability of an apparatus is deteriorated due to outbreak of cracks in a connection part by the effect of thermal stress on a bump of a semiconductor element, when a semiconductor device having a plurality of semiconductor elements is bump-connected to a resin substrate. SOLUTION: In a packaging structure of an electronic component, the semiconductor device which includes a plurality of lands and bumps on a rear of an interposer wiring substrate loading the plurality of semiconductor elements is connected to the resin substrate that has the plurality of lands arrayed; the bump in a position and the circumference where the bump is arrayed at a position farthest from the center of the semiconductor device among the bumps, at a position where the bumps are superimposed on the semiconductor elements of the interposer wiring substrate is parallel-connected to bumps adjacent to the bumps, whereby the bump at a position where the stress concentration occurs most frequently is redundant-connected; and the other bump is kept connected even if one bump is fractured, thereby drafting a period, until a failure occurs. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011159840(A) 申请公布日期 2011.08.18
申请号 JP20100020865 申请日期 2010.02.02
申请人 PANASONIC CORP 发明人 FUJIMOTO MITSUTERU;WATANABE MASAKI
分类号 H01L21/60;H01L23/32 主分类号 H01L21/60
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