| 摘要 |
PROBLEM TO BE SOLVED: To prevent a reduction in accuracy of a load test of a load transistor in a semiconductor memory device. SOLUTION: The semiconductor memory device includes: a plurality of SRAM cells (30, 31 and the like) arranged in a grid to store data; a plurality of bit line pairs (BL0T, BL0B and the like) for connecting the SRAM cells disposed in a row direction; a write amplifier 51 for writing data in the SRAM cells; and a soft-write circuit 10 connected to at least one of the plurality of bit line pairs to pull a predetermined current from the connected bit line according to a test control signal TEST. The soft-write circuit 10 includes a current mirror circuit having first transistors N31 and N33 for outputting branch current, and a second transistor N35 to which original current is input. The original current is generated by a replica transistor formed by the same process as that of the load transistor of the SRAM cell. COPYRIGHT: (C)2011,JPO&INPIT
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