发明名称 LOGIC SIMULATOR AND LOGIC VERIFICATION PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a logic simulator and a logic verification program, which can enhance efficiency of verification work. SOLUTION: A plurality of simulation databases is formed to correspond respectively to a plurality of logic circuits, and pieces of initial state setting information of respective elements required for constituting the plurality of logic circuits are held individually in the respective formed simulation databases. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011159293(A) 申请公布日期 2011.08.18
申请号 JP20110016982 申请日期 2011.01.28
申请人 TOSHIBA CORP;TOSHIBA TEC CORP 发明人 FUJITA YUTAKA
分类号 G06F17/50;G06F11/25 主分类号 G06F17/50
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