| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce jitter of a clock pulse in one clock pulse unit, in real time. <P>SOLUTION: A clock output circuit for reducing jitter included in a clock pulse includes: a delaying part for generating a plurality of delay clock pulses having different phases from an input clock pulse (input clock pulse); a period measuring part for measuring the period of each pulse of the input clock pulse; an accumulation operating part for accumulatingly operating each period measured by the period measuring part to obtain an accumulated operation value; a target accumulation operating part for accumulatingly operating the period (target period) of a targeted clock pulse to obtain a target accumulation operation value; a difference operating part for comparing the accumulation operation value with the target accumulation operation value to obtain a difference value in each period of the clock pulse; and a selecting part for selecting a delay clock pulse wherein the influence of the difference value is offset by referring to the difference value from the delaying part, and outputting the delay clock pulse as an output clock pulse. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
