| 摘要 |
A PLL circuit is provided capable of reducing phase noise and facilitating design. In the PLL circuit, a PLL receives a reference frequency and an output from a VC-TCXO, performs a lock operation. In a lock state, a selector selects an output of a first divider that divides the reference frequency. When PLL detects input of reference frequency being lost or an unlock state, the PLL outputs an alarm signal to the selector. When receiving the alarm signal from the PLL, the selector switches from the output of the first divider to an output of a second divider that frequency-divides an output of the VC-TCXO, and outputs the same. Then, a PLL receives an output of the selector and an output of a VCXO and performs a lock operation.
|
