发明名称 A LEVEL TRANSLATION CIRCUIT
摘要 The present invention relates to a level translation circuit (1) which is connected between two buses (B1, B2), whereto more than one circuit is connected by open drain or open collector output, and which decreases the capacitive effect and the effect of the signal waveform distortions by reproducing the signal level of one of the buses (B1 or B2) at the other bus (B2 or B1).
申请公布号 EP2356746(A1) 申请公布日期 2011.08.17
申请号 EP20090749133 申请日期 2009.11.12
申请人 ARCELIK ANONIM SIRKETI 发明人 BASARAN, FAHRETTIN
分类号 H03K19/018;G06F13/40 主分类号 H03K19/018
代理机构 代理人
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