发明名称
摘要 <p>The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.</p>
申请公布号 JP4749089(B2) 申请公布日期 2011.08.17
申请号 JP20050246408 申请日期 2005.08.26
申请人 发明人
分类号 G11C11/41;G01R31/28;G01R31/3185;G11C11/401;G11C29/14;H01L21/8244;H01L27/10;H01L27/11 主分类号 G11C11/41
代理机构 代理人
主权项
地址