发明名称 Multilayer wiring structure, semiconductor device, pattern transfer mask and method for manufacturing multilayer wiring structure
摘要 A multilayer interconnection structure according to this invention is applied to a case where a plurality of interconnections are formed at a fine pitch and a via is connected to at least one of the interconnections. In the multilayer interconnection structure, a region facing the via is locally narrowed in at least the interconnection, facing the via, of the interconnections adjacent to the interconnection connected to the via.
申请公布号 US7999392(B2) 申请公布日期 2011.08.16
申请号 US20060908099 申请日期 2006.03.09
申请人 RENESAS ELECTRONICS CORPORATION 发明人 OHTAKE HIROTO;HAYASHI YOSHIHIRO
分类号 H01L23/48;H01L23/52;H01L29/40;H05K1/11 主分类号 H01L23/48
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