发明名称 |
Scan testing architectures for power-shutoff aware systems |
摘要 |
In a circuit adapted for scan testing, a first set of connections configures the circuit elements into power domains with separate power-level controls, and a second set of connections configures the circuit elements to form scan segments for loading values into circuit elements from input ends of the scan segments and unloading values from circuit elements at output ends of the scan segments. A decompressor circuit receives a decompressor input and is operatively connected to the scan-segment input ends, and a compressor circuit is operatively connected to the scan segment output ends and generates a compressor output. Isolation circuits at scan-segment exits set values for scan segments at scan-segment exits when a corresponding independent power domain is in a power-off state.
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申请公布号 |
US8001433(B1) |
申请公布日期 |
2011.08.16 |
申请号 |
US20080345950 |
申请日期 |
2008.12.30 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
BHATIA SANDEEP;GALLAGHER PATRICK;FOUTZ BRIAN;CHICKERMANE VIVEK |
分类号 |
G01R31/28;G06F17/50 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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