CDR CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a compact low-power CDR (clock data recovery) circuit which has instantaneous response characteristics to input data and reduces output jitter even when data with high jitter is input.

SOLUTION: The CDR circuit includes: a VCO 11 for adjusting the phase of an output clock so as to be synchronized with input data 4; a VCO 13 for adjusting the phase of a reproduction clock 7 so as to be synchronized with the output clock of the VCO 11; a frequency comparator 2 and a VCO 12 as frequencies control circuits for generating a control signal 8 for controlling the oscillation frequency of the VCOs 11, 13; and an attenuator 30 inserted between an output terminal of the VCO 11 and an input terminal of the VCO 13.

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