发明名称 |
SEMICONDUCTOR WAFER CHIP SCALE PACKAGE TEST FLOW AND DICING PROCESS |
摘要 |
A method for forming a semiconductor device can include electrically testing a plurality of semiconductor dies in wafer form subsequent to performing a first wafer dicing process, then performing a second wafer dicing process to dice the wafer and to singularize the plurality of semiconductor dies. Electrically testing the plurality of semiconductor dies in wafer form subsequent to the first dicing process can identify chips damaged during the first dicing process. The method can also include forming a plurality of grooves between adjacent dies which leaves a full wafer thickness at a perimeter of the wafer to result in a wafer which is more resistant to deflection and damage during handling.
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申请公布号 |
US2011193200(A1) |
申请公布日期 |
2011.08.11 |
申请号 |
US20100881845 |
申请日期 |
2010.09.14 |
申请人 |
LYNE KEVIN P;BEDDINGFIELD STANLEY CRAIG;DE OBALDIA ELIDA I;CAMENFORTE RAYMUNDO MONASTERIO;STEPNIAK DAVID CHARLES |
发明人 |
LYNE KEVIN P.;BEDDINGFIELD STANLEY CRAIG;DE OBALDIA ELIDA I.;CAMENFORTE RAYMUNDO MONASTERIO;STEPNIAK DAVID CHARLES |
分类号 |
H01L23/544;H01L21/304;H01L21/66 |
主分类号 |
H01L23/544 |
代理机构 |
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地址 |
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