5-TRANSISTOR NON-VOLATILE MEMORY CELL

摘要

A method is provided for programming a non-volatile memory (NVM) cell array that includes a plurality of NVM cells. Each NVM cell in the array includes an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node, a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the storage node, an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the storage node, the bulk region electrode being connected to a common bulk node, a first NMOS pass gate transistor having a source electrode connected to the drain electrode of the NMOS data transistor, a drain electrode connected to a first array bit line, a bulk region electrode connected to the common bulk node and a gate electrode connected to a first array word line, and a second NMOS pass gate transistor having a drain electrode connected to the source electrode of the NMOS data transistor, a source electrode connected to a second array bit line, a bulk region electrode connected to the common bulk node and a gate electrode connected to a second array word line. The NVM cell array programming method comprises: for each NVM cell in the NVM cell array, setting the source, drain, bulk region and gate electrodes of the NMOS control transistor, the PMOS erase transistor and the NMOS data transistor of the NVM cell to 0V; for each cell in the array selected for programming, setting either the first array word line to a positive inhibiting voltage while setting the first bit line to 0V, or setting the second array word line to the positive inhibiting voltage while setting the second bit line to 0V, or both, while setting the common bulk node to 0V; for each cell in the array not selected for programming, setting the first and second array word lines to 0V while setting the first or second array bit line (or both) to the positive inhibiting voltage or 0V while setting the common bulk node to 0v; ramping up the control voltage from 0V to a maximum positive control voltage and the erase voltage from 0V to a maximum positive erase voltage for a programming time period; ramping down the control voltage from the maximum positive control voltage to 0V and the erase voltage from the maximum positive erase voltage to 0V; and returning all electrodes in the array that are set to the positive inhibiting voltage to 0V.