| 摘要 |
A memory circuit is disclosed. The memory circuit includes memory cells and asynchronous read decode logic configured to decode a received address and to select particular ones of the memory cells for reading. The read decode logic may be comprised of static, combinational logic, and thus the decoding of the received address may be conducted without the use of a clock signal or a cycle of a clock signal. Accordingly, a read operation may be conducted responsive to receiving the read address, without waiting for a subsequent clock edge. Furthermore, read output logic may also be asynchronous, and thus may provide data read from the memory cells without having to wait for a clock edge. The read output logic may include push-pull driver circuits coupled to global bit lines. The push-pull driver circuits may drive their corresponding global bit lines based on the data read from corresponding memory cells.
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