| 摘要 |
The number of wirings per unit memory cell is reduced by sharing a bit line by a writing transistor and a reading transistor. Data is written by turning on the writing transistor so that a potential of the bit line is supplied to a node where one of a source electrode and a drain electrode of the writing transistor and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined amount of charge is held in the node. Data is read by using a reading signal line connected to one of a source electrode and a drain electrode of the reading transistor so that a predetermined reading potential is supplied to the reading signal line, and then detecting a potential of the bit line. |
