发明名称 Reception circuit, information processing device, and buffer control method
摘要 A reception circuit (301) that receives data in serial communications through a plurality of lanes includes a plurality of buffers (314) provided for each of the plurality of lanes, each of which stores data received through a corresponding lane. A multilane control circuit (303) detects the skew between the lanes, and outputs an adjustment instruction for adjusting a read address of a buffer and deskew information indicating that a skew adjustment between the lanes is to be performed based on the detected skew. A plurality of address control circuits (315) are provided for each of the plurality of lanes, each of which transmits the adjustment instruction to a corresponding buffer when receiving the deskew information, wherein the buffer (314) that has received the adjustment instruction adjusts its read address.
申请公布号 EP2355431(A1) 申请公布日期 2011.08.10
申请号 EP20110150819 申请日期 2011.01.13
申请人 FUJITSU LIMITED 发明人 IWATSUKI, RYUJI;HAYASAKA, KAZUMI
分类号 H04L25/14;H04L7/08 主分类号 H04L25/14
代理机构 代理人
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