| 摘要 |
A single pulse shaper with pulses of fixed length equal to two clock cycles, with adjustable pulse delay comprises a reversible binary countdown counter having clock input, integrating/countdown set input, synchronous parallel load enable input, loading data inputs, computing enable input, asynchronous reset input, overflow input, two-input elements OR, an inverter, a circuit comprising in series connected a resistor and a capacitor, a start/stop device comprising synchronous flip-flop having asynchronous reset input, first and second two-input elements AND, three-input element OR. In addition, two JK-triggers are incorporated with asynchronous reset input, a second two-input element OR, third two-input element AND, output of which serves as output of the shaper. |
